<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:content="http://purl.org/rss/1.0/modules/content/"><channel><title>Posts on Indian MLOps and LLMOps Group</title><link>https://indianmlopsgroup.org/blogs/</link><description>Recent content in Posts on Indian MLOps and LLMOps Group</description><generator>Hugo</generator><language>en-us</language><copyright>2026 Indian MLOps and LLMOps Group</copyright><lastBuildDate>Thu, 06 Aug 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://indianmlopsgroup.org/blogs/index.xml" rel="self" type="application/rss+xml"/><item><title>RISC-V and the Supply Side of AI: Why an MLOps Community Should Care About Silicon</title><link>https://indianmlopsgroup.org/blogs/riscv-supply-side-of-ai/</link><pubDate>Sat, 04 Jul 2026 00:00:00 +0530</pubDate><guid>https://indianmlopsgroup.org/blogs/riscv-supply-side-of-ai/</guid><description>How RISC-V, chiplets, and UCIe are reshaping the AI hardware supply chain — and why India&amp;#39;s MLOps community should pay attention.</description></item><item><title>RISC-V/RVV at the Edge: From PyTorch to vsetvli</title><link>https://indianmlopsgroup.org/blogs/risc-v-rvv-edge-inference/</link><pubDate>Thu, 06 Aug 2026 00:00:00 +0000</pubDate><guid>https://indianmlopsgroup.org/blogs/risc-v-rvv-edge-inference/</guid><description>Triton is early, LLVM is real. A field guide to how models trained in PyTorch and TensorFlow actually reach RISC-V/RVV silicon — VLEN, LMUL, the SpacemiT K1/K3, the India gap, and why MQTT is quietly becoming the edge-AI control plane.</description></item></channel></rss>