Posts

Most of us in the MLOps world spend our days one or two layers above silicon — pipelines, GPUs-as-a-service, model serving, observability. It’s easy to treat the chip underneath as a black box that “just works.” But every argument we make about scaling AI in India — more inference, more fine-tuning, more sovereign models — eventually runs into a hard wall: how much compute exists, who controls its design, and what it costs. That wall is made of silicon, and right now it is being redrawn by an open standard called RISC-V. ...

A SpacemiT board lands on your desk. Somewhere on it, silicon markets itself as RVV 1.0. You have a PyTorch checkpoint. Somewhere between the two sits a genuinely interesting question that most MLOps content skips entirely: how does a tensor operation you wrote in Python actually become a vector instruction on a RISC-V core? Not “can you run inference on RISC-V” — you can, apt install and go. The real question is what happens in between: which compiler owns that translation, whether OpenAI’s Triton has any business being in this conversation yet, and what the vector extension itself is actually doing differently from the CUDA model most of us think in by default. ...